7427 4L80E PCS control dithering
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7427 4L80E PCS control dithering
What is known about the dithering requirement on the early 4l80E PCS (force motor)? Is it something we need for reliability sake? Is there a way to get this in the $0E mask? Maybe it's already there, I'm just not seeing it.
From the MS manual...
From the MS manual...
The Pressure Control solenoid controls main line pressure, pulsed at 0-60% duty cycles at 293 Hz. There is a cleaning pulse (dither) every 10 seconds on this transmission (Early 4L80E). Late 4L80E was changed to 614 Hz and the cleaning pulse (dither) was omitted.
PWM Refresh and Dithering
Some PWM solenoids uses a deliberately low PWM percent, but refresh the solenoid with a burst at 100% before it can close. As well, some pressure control solenoids use a cleaning pulse (called a 'dither') to ensure adequate fluid flow through the system to keep the system clean. You can set both of these up in this dialog.
PWM Refresh Interval: the time, in milliseconds, between refresh pulses on output1, output2, and output4.
PWM Refresh Duration: the time, in milliseconds, that refresh pulses are held high (100% duty cycle) on output1, output2, and output4, set to zero to disable,
PC Dither Interval: the time, in milliseconds, between dither pulses on the PC output (processor pin PT2 on circuit PWM3 using Ampseal pin 33),
PC Dither Duration: the time, in milliseconds, that refresh pulses are held high (100% duty cycle) on the PC output = solC (processor pin PT2 on circuit PWM3 using Ampseal pin 33), set to zero to disable.
PWM Refresh and Dithering
Some PWM solenoids uses a deliberately low PWM percent, but refresh the solenoid with a burst at 100% before it can close. As well, some pressure control solenoids use a cleaning pulse (called a 'dither') to ensure adequate fluid flow through the system to keep the system clean. You can set both of these up in this dialog.
PWM Refresh Interval: the time, in milliseconds, between refresh pulses on output1, output2, and output4.
PWM Refresh Duration: the time, in milliseconds, that refresh pulses are held high (100% duty cycle) on output1, output2, and output4, set to zero to disable,
PC Dither Interval: the time, in milliseconds, between dither pulses on the PC output (processor pin PT2 on circuit PWM3 using Ampseal pin 33),
PC Dither Duration: the time, in milliseconds, that refresh pulses are held high (100% duty cycle) on the PC output = solC (processor pin PT2 on circuit PWM3 using Ampseal pin 33), set to zero to disable.
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Damon
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09-26-2015 04:29 PM